1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor device including a high-frequency circuit having an inductor.
2. Description of the Background Art
With reference to FIG. 68, an example of constructions of a semiconductor device including a high-frequency circuit is described below. FIG. 68 is a block diagram showing a construction of a semiconductor device 90 having the function of receiving a radio wave signal of a radio frequency (10 kHz to 100 GHz) to output an audio signal.
As illustrated in FIG. 68, the semiconductor device 90 comprises an RF circuit portion 91 for demodulating the received radio wave signal, a logic portion 92 for processing the signal demodulated by the RF circuit portion 91 to convert the processed signal into the audio signal, and a memory cell portion 93 for storing therein data required for the RF circuit portion 91 and the logic portion 92 to perform the signal processing. The semiconductor device 90 is connected to an antenna device 94 for detecting the radio wave signal, and a sound output device 95 for outputting the audio signal.
The so-called high-frequency circuit, including the RF circuit portion 91, has an inductor (inductance element) in addition to a resistor and a capacitor. The inductor which functions to advance the phase of a high-frequency current may be used against a capacitor which functions to delay the phase of the high-frequency current, thereby to provide matching of the high-frequency current.
An inductor L1 in the RF circuit portion 91 is shown in FIG. 68. The inductor L1 has a parasitic capacitor C1 grounded through a resistor R1. The resistor R1 is a resistor of a semiconductor substrate which forms the RF circuit portion 91. There is no problem when the resistor R1 has an extremely low resistance or an extremely high resistance. However, some substrates have a resistance (e.g., about 10 xcexa9cm) which causes power consumption because of electrostatically induced power dissipation.
FIG. 69 shows a construction for preventing such electrostatically induced power dissipation. In the construction shown in FIG. 69, the parasitic capacitor C1 is not only grounded through the resistor R1 but also grounded through a resistor R2. The resistor R2 has a resistance extremely lower than that of the resistor R1. The high-frequency current predominantly flows to the ground through the resistor R2 to cause no electrostatically induced power dissipation.
The inductor L1 is shown as having an end A connected to the antenna device 94, and an end B connected to a source/drain electrode of a MOS transistor Q1. This is an example of inductor connections.
The resistor R2 is a conductor plate known as a shield plate, and is disposed in an underlying layer of the inductor L1. FIG. 70 is a perspective view showing a construction of the inductor L1 and the shield plate.
As illustrated in FIG. 70, the inductor L1 is formed of a wire wound in a spiral form and is thus referred to hereinafter as a spiral inductor SI. The center of the spiral which is a first end of the spiral inductor SI is connected to an underlying interconnect line WL through a contact portion CP extending through an interlayer insulation film not shown. The interconnect line WL is disposed on an interlayer insulation film SZ which covers a semiconductor substrate SB.
The interconnect line WL corresponds to the end B of the inductor L1 shown in FIG. 69, and the end A corresponds to a second end of the spiral inductor SI.
The semiconductor substrate SB is an SOI (silicon on insulator) substrate, which is shown in FIG. 70 as comprising only an SOI layer SL and an isolation oxide film FZ in the SOI layer SL. On the isolation oxide film FZ, a planar shield plate SP having an area at least equal to the area occupied by the spiral inductor SI, as viewed in plan, is disposed in a position corresponding to a region in which the spiral inductor SI is formed.
The shield plate SP is made of a low-resistance conductor similar to the material of the interconnect line, and is grounded through an interconnect line not shown to cause no electrostatically induced power dissipation.
However, current flowing in the spiral inductor SI generates an eddy current inside the shield plate SP to increase electromagnetically induced power dissipation, presenting another problem of the increase in total power dissipation.
To solve the problem, there has been proposed a perforated ground shield (referred to hereinafter as a PG shield) which is a shield plate with portions cut away to interrupt the path of the eddy current.
FIG. 71 shows an example of the PG shield. The PG shield shown in FIG. 71 comprises a plurality of plates PL electrically insulated from each other. The plates PL are triangular in plan configuration, and are arranged radially so that their apexes constitute a central part of the PG shield.
The use of such a construction interrupts the path of the eddy current to reduce the electromagnetically induced power dissipation.
As described above, the background art semiconductor device having the inductor uses the PG shield to reduce the electrostatically induced power dissipation and the electromagnetically induced power dissipation. However, the formation of the PG shield requires one additional conductor layer to be provided, resulting in the increase in structural complexity and the number of manufacturing steps.
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; a shield layer disposed in a main surface of the semiconductor substrate; and an inductance element disposed over a region in which the shield layer is formed, with an interlayer insulation film therebetween, wherein the shield layer has at least one conductive portion connected to a ground potential, and at least one current interrupting portion for interrupting a path of an eddy current induced by the inductance element in a plane of the at least one conductive portion.
Preferably, according to a second aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on the substrate portion, and an SOI layer disposed on the buried oxide film. The at least one current interrupting portion comprises a plurality of selectively disposed isolation oxide films extending from a surface of the SOI layer through the SOI layer to the buried oxide film. The at least one conductive portion comprises a plurality of SOI regions electrically isolated from each other by the plurality of isolation oxide films.
Preferably, according to a third aspect of the present invention, in the semiconductor device of the second aspect, each of the plurality of isolation oxide films has a predetermined width and extends substantially perpendicularly to a surface of the buried oxide film.
Preferably, according to a fourth aspect of the present invention, in the semiconductor device of the second aspect, each of the plurality of isolation oxide films includes a first portion having a first width and extending substantially perpendicularly to a surface of the buried oxide film, and a second portion continuous with and beneath the first portion, the second portion having a second width smaller than the first width and extending substantially perpendicularly to the surface of the buried oxide film.
Preferably, according to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on the substrate portion, and an SOI layer disposed on the buried oxide film. The at least one conductive portion comprises a plurality of SOI regions obtained by thinning the SOI layer to a predetermined thickness. The at least one current interrupting portion comprises an insulation film disposed to at least fill a space between the plurality of SOI regions.
Preferably, according to a sixth aspect of the present invention, in the semiconductor device of the fifth aspect, each of the plurality of SOI regions contains a semiconductor impurity of a relatively high concentration.
Preferably, according to a seventh aspect of the present invention, in the semiconductor device of the fifth aspect, each of the plurality of SOI regions has a silicide film formed on an upper surface thereof.
Preferably, according to an eighth aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on the substrate portion, and an SOI layer disposed on the buried oxide film. The shield layer comprises a first group of SOI regions of a first conductivity type, and a second group of SOI regions of a second conductivity type, the first group of SOI regions and the second group of SOI regions being combined to constitute a plurality of diodes. The at least one current interrupting portion includes at least one reverse-biased diode which is at least one of the plurality of diodes to which a reverse bias is applied. The at least one conductive portion includes one of the first and second groups connected to a ground potential.
Preferably, according to a ninth aspect of the present invention, in the semiconductor device of the eighth aspect, the first group of SOI regions and the second group of SOI regions are formed in a region obtained by thinning the SOI layer to a predetermined thickness. The semiconductor device further comprises an isolation oxide film for entirely covering the first group of SOI regions and the second group of SOI regions.
Preferably, according to a tenth aspect of the present invention, in the semiconductor device of the eighth aspect, each of the first group of SOI regions includes a first region approximately equal in thickness to the SOI layer, and a second region adjacent to the first region and obtained by thinning the SOI layer. Each of the second group of SOI regions is approximately equal in thickness to the SOI layer. The semiconductor device further comprises an isolation oxide film for covering an upper surface of each of the second regions.
Preferably, according to an eleventh aspect of the present invention, in the semiconductor device of the tenth aspect, each of the first regions of the first group of SOI regions and the second group of SOI regions has a silicide film formed on an upper surface thereof.
Preferably, according to a twelfth aspect of the present invention, in the semiconductor device of the eighth aspect, each of the first group of SOI regions is a region obtained by thinning the SOI layer to a predetermined thickness. Each of the second group of SOI regions is approximately equal in thickness to the SOI layer. The first group of SOI regions and the second group of SOI regions are adjacent to each other. The semiconductor device further comprises an isolation oxide film for individually covering the first group of SOI regions.
Preferably, according to a thirteenth aspect of the present invention, in the semiconductor device of the twelfth aspect, each of the second group of SOI regions has a silicide film formed on an upper surface thereof.
Preferably, according to a fourteenth aspect of the present invention, in the semiconductor device of the twelfth aspect, the second group of SOI regions are of a rectangular plan configuration. The shield layer is of a plan configuration in which the second group of SOI regions are arranged in a matrix, with the isolation oxide film therebetween.
Preferably, according to a fifteenth aspect of the present invention, in the semiconductor device of the twelfth aspect, the second group of SOI regions are electrically connected to each other by a gate interconnect line similar in construction to a gate electrode of a MOS transistor.
Preferably, according to a sixteenth aspect of the present invention, in the semiconductor device of the eighth aspect, the first group of SOI regions and the second group of SOI regions are arranged in an alternating pattern. A gate structure of a MOS transistor is disposed on each of the first group of SOI regions.
Preferably, according to a seventeenth aspect of the present invention, in the semiconductor device of the eighth aspect, the first group of SOI regions and the second group of SOI regions are arranged in an alternating pattern. Each of the first group of SOI regions includes a first region and a second region adjacent to the first region. A gate structure of a MOS transistor is disposed on each of the second regions.
Preferably, according to an eighteenth aspect of the present invention, in the semiconductor device of the eighth aspect, the first group of SOI regions and the second group of SOI regions are arranged in an alternating pattern. Each of the first group of SOI regions includes a first region and a second region adjacent to the first region. Each of the second group of SOI regions and the first regions has a silicide film formed thereon selectively for non-engagement with the second regions.
Preferably, according to a nineteenth aspect of the present invention, in the semiconductor device of the eighth aspect, the first group of SOI regions and the second group of SOI regions are arranged in an alternating pattern. Each of the first group of SOI regions has a silicide film formed thereon selectively for non-engagement with the second group of SOI regions.
Preferably, according to a twentieth aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on the substrate portion, and an SOI layer disposed on the buried oxide film. The substrate portion comprises an eddy current suppressing portion for suppressing the generation of an eddy current induced by the inductance element, the eddy current suppressing portion being disposed in a region corresponding to at least a region in which the inductance element is formed, the eddy current suppressing portion having at least one hollow structure formed therein.
Preferably, according to a twenty-first aspect of the present invention, in the semiconductor device of the twentieth aspect, the eddy current suppressing portion comprises a cavity having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the cavity being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed.
Preferably, according to a twenty-second aspect of the present invention, in the semiconductor device of the twentieth aspect, the eddy current suppressing portion comprises a porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed.
Preferably, according to a twenty-third aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on the substrate portion, and an SOI layer disposed on the buried oxide film. The SOI layer comprises a porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least a region in which the inductance element is formed.
Preferably, according to a twenty-fourth aspect of the present invention, in the semiconductor device of the first aspect, the semiconductor substrate comprises a porous layer disposed in a region corresponding to a region in which the inductance element is formed, the porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed.
Preferably, according to a twenty-fifth aspect of the present invention, in the semiconductor device of any one of the twenty-second to twenty-fourth aspects, the porous layer comprises a plurality of holes or trenches formed by etching or a plurality of holes formed by an anodization process.
Preferably, according to a twenty-sixth aspect of the present invention, the semiconductor device of the second aspect further comprises a plurality of trenches disposed under the plurality of isolation oxide films and extending through the buried oxide film into the substrate portion.
Preferably, according to a twenty-seventh aspect of the present invention, the semiconductor device of the fifth aspect further comprises a plurality of trenches disposed under the insulation film disposed between the plurality of SOI regions and extending through the buried oxide film into the substrate portion.
Preferably, according to a twenty-eighth aspect of the present invention, in the semiconductor device of the first aspect, the at least one current interrupting portion comprises a plurality of isolation oxide films extending from the surface of the semiconductor substrate to a predetermined depth. The at least one conductive portion comprises a plurality of substrate regions divided by the plurality of isolation oxide films. The semiconductor device further comprises a plurality of trenches reaching a predetermined depth in the semiconductor substrate.
Preferably, according to a twenty-ninth aspect of the present invention, in the semiconductor device of the twenty-fifth aspect, the plurality of holes or trenches are filled with a near-vacuum.
Preferably, according to a thirtieth aspect of the present invention, in the semiconductor device of any one of the twenty-sixth to twenty-eighth aspects, the plurality of trenches are filled with a near-vacuum.
According to a thirty-first aspect of the present invention, a semiconductor device comprises: a semiconductor substrate; and a shield layer disposed in a main surface of the semiconductor substrate under and longitudinally of an interconnect layer, the shield layer including a plurality of conductive portions spaced apart from each other longitudinally of the interconnect layer and connected to a ground potential, and a plurality of insulation portions disposed between the plurality of conductive portions.
Preferably, according to a thirty-second aspect of the present invention, in the semiconductor device of the thirty-first aspect, each of the plurality of conductive portions comprises a plurality of conductor films and a plurality of insulation films stacked in an alternating pattern.
A thirty-third aspect of the present invention is intended for a method of manufacturing a semiconductor device having an inductance element. According to the present invention, the method comprises the steps of: (a) preparing an SOI substrate including a substrate portion serving as a foundation, a buried oxide film disposed on the substrate portion, and an SOI layer disposed on the buried oxide film; (b) forming an opening extending through at least the SOI layer and the buried oxide film to the substrate portion; and (c) introducing a solution of KOH into the opening to etch the substrate portion, thereby forming a cavity having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the cavity being approximately coextensive, as viewed in plan, with at least a region in which the inductance element is to be formed.
A thirty-fourth aspect of the present invention is intended for a method of manufacturing a semiconductor device having an inductance element. According to the present invention, the method comprises the steps of: (a) preparing a first silicon substrate to form a porous layer in a main surface of the first silicon substrate, the porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least a region in which the inductance element is to be formed; (b) preparing a second silicon substrate to form a silicon oxide film on a main surface of the second silicon substrate; (c) bonding the first silicon substrate and the second silicon substrate together so that the main surface of the first silicon substrate in which the porous layer is formed and the silicon oxide film of the second silicon substrate are in face-to-face relation, the first silicon substrate being used as a substrate portion, the silicon oxide film being used as a buried oxide film, and then thinning the second silicon substrate to a predetermined thickness by polishing to form an SOI layer; and (d) forming the inductance element over a region in which the porous layer is formed.
A thirty-fifth aspect of the present invention is intended for a method of manufacturing a semiconductor device having an inductance element. According to the present invention, the method comprises the steps of: (a) preparing a first silicon substrate to form a silicon oxide film on a main surface of the first silicon substrate; (b) preparing a second silicon substrate to form a porous layer in a main surface of the second silicon substrate, the porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least a region in which the inductance element is to be formed; (c) bonding the first silicon substrate and the second silicon substrate together so that the silicon oxide film of the first silicon substrate and the main surface of the second silicon substrate in which the porous layer is formed are in face-to-face relation, the first silicon substrate being used as a substrate portion, the silicon oxide film being used as a buried oxide film, and then thinning the second silicon substrate to a predetermined thickness by polishing to form an SOI layer in conjunction with the porous layer; and (d) forming the inductance element over a region in which the porous layer is formed.
Preferably, according to a thirty-sixth aspect of the present invention, in the method of the thirty-fourth or thirty-fifth aspect, the step (a) comprises the steps of: (a-1) forming a plurality of holes or trenches in the main surface of the first silicon substrate by etching to constitute the porous layer; and (a-2) covering an opening of each of the plurality of holes or trenches with an insulation film, with the interior of each of the plurality of holes or trenches rendered hollow.
Preferably, according to a thirty-seventh aspect of the present invention, in the method of the thirty-fourth or thirty-fifth aspect, the step (a) comprises the steps of: (a-1) forming a plurality of holes or trenches in the main surface of the first silicon substrate by etching to constitute the porous layer; and (a-2) performing an anneal in a hydrogen atmosphere to remove an opening of each of the plurality of holes or trenches by reduction, with the interior of each of the plurality of holes or trenches rendered hollow.
Preferably, according to a thirty-eighth aspect of the present invention, in the method of the thirty-fourth or thirty-fifth aspect, the step (a) comprises the steps of: (a-1) forming a plurality of holes in the main surface of the first silicon substrate by an anodization process to constitute the porous layer; and (a-2) covering an opening of each of the plurality of holes with an insulation film, with the interior of each of the plurality of holes rendered hollow.
Preferably, according to a thirty-ninth aspect of the present invention, in the method of the thirty-fourth or thirty-fifth aspect, the step (a) comprises the steps of: (a-1) forming a plurality of holes in the main surface of the first silicon substrate by an anodization process to constitute the porous layer; and (a-2) performing an anneal in a hydrogen atmosphere to remove an opening of each of the plurality of holes by reduction, with the interior of each of the plurality of holes rendered hollow.
In accordance with the first aspect of the present invention, the semiconductor device comprises the shield layer disposed in the main surface of the semiconductor substrate, the shield layer having the at least one conductive portion connected to the ground potential, and the at least one current interrupting portion for interrupting the path of the eddy current induced by the inductance element such as a spiral inductor in a plane of the at least one conductive portion. Therefore, the semiconductor device of the first aspect can reduce electrostatically induced power dissipation, and interrupt the path of the eddy current in the shield layer to reduce electromagnetically induced power dissipation. Additionally, the shield layer which is formed in the semiconductor substrate may be formed, for example, in the step of forming a MOS transistor at the same time. Therefore, no additional conductor layer is required to form the shield layer, and the device structure is not complicated.
In the semiconductor device according to the second aspect of the present invention, the at least one current interrupting portion comprises the plurality of isolation oxide films extending to the buried oxide film, and the at least one conductive portion comprises the plurality of SOI regions electrically isolated from each other by the plurality of isolation oxide films. Current flows through the plurality of SOI regions, whereby the electrostatically induced power dissipation is reduced. The isolation oxide films interrupt the path of the eddy current to avoid the electromagnetically induced power dissipation resulting from the eddy current.
In the semiconductor device according to the third aspect of the present invention, each of the plurality of isolation oxide films has a predetermined width and is shaped to extend substantially perpendicularly to the surface of the buried oxide film. This is known as a complete isolation oxide film. Therefore, the plurality of isolation oxide films may be formed simultaneously with device isolation in a portion where a MOS transistor is formed by using the complete isolation oxide film, and a method of manufacturing the semiconductor device is not complicated.
In the semiconductor device according to the fourth aspect of the present invention, each of the plurality of isolation oxide films includes the first portion having the first width and extending substantially perpendicularly to the surface of the buried oxide film, and the second portion continuous with and beneath the first portion, the second portion having the second width smaller than the first width and extending substantially perpendicularly to the surface of the buried oxide film. Thus, the plurality of isolation oxide films are formed in the step of manufacturing a so-called partial isolation oxide film. Therefore, the plurality of isolation oxide films may be formed simultaneously with device isolation in a portion where a MOS transistor is formed by using the partial isolation oxide film, and a method of manufacturing the semiconductor device is not complicated.
In the semiconductor device according to the fifth aspect of the present invention, the at least one conductive portion comprises the plurality of SOI regions obtained by thinning the SOI layer to the predetermined thickness, and the at least one current interrupting portion comprises the insulation film disposed to at least fill the space between the plurality of SOI regions. Current flows through the plurality of SOI regions, whereby the electrostatically induced power dissipation is reduced. The insulation film interrupts the path of the eddy current to avoid the electromagnetically induced power dissipation resulting from the eddy current. Additionally, since the at least one conductive portion is formed by dividing the SOI layer, no additional conductor layer is required to form the shield layer, and the device structure is not complicated.
In the semiconductor device according to the sixth aspect of the present invention, each of the plurality of SOI regions contains the semiconductor impurity of the relatively high concentration. Therefore, the SOI regions having a low resistance are provided.
In the semiconductor device according to the seventh aspect of the present invention, each of the plurality of SOI regions has the silicide film formed on the upper surface thereof. Therefore, the SOI regions having a low resistance are provided.
In the semiconductor device according to the eighth aspect of the present invention, the at least one current interrupting portion includes at least one reverse-biased diode which is at least one of the plurality of diodes to which a reverse bias is applied, and the at least one conductive portion includes one of the first and second groups of the SOI regions connected to the ground potential. The presence of the at least one reverse-biased diode prevents the diodes from being forward-biased by a counter electromotive force which generates the eddy current, to interrupt the eddy current, thereby avoiding the electromagnetically induced power dissipation resulting from the eddy current. Additionally, since the at least one current interrupting portion and the at least one conductive portion are formed by dividing the SOI layer, no additional conductor layer is required to form the shield layer, and the device structure is not complicated.
In the semiconductor device according to the ninth aspect of the present invention, the first group of SOI regions, the second group of SOI regions and the isolation oxide film thereon constitute a so-called partial isolation structure, which may be formed simultaneously with device isolation, for example, in a portion where a MOS transistor is formed by using the partial isolation, and a method of manufacturing the semiconductor device is not complicated. Additionally, when device isolation is performed in the portion where the MOS transistor is formed by using the partial isolation, the potential of a channel region can be fixed through a well region under the partial isolation oxide film. Therefore, various problems resulting from a floating-substrate effect are prevented.
In the semiconductor device according to the tenth aspect of the present invention, the isolation oxide film which is formed only on the second regions is small in area, to prevent the generation of dishing during the manufacture.
In the semiconductor device according to the eleventh aspect of the present invention, each of the first regions of the first group of SOI regions and the second group of SOI regions has the silicide film formed on the upper surface thereof. Therefore, the SOI regions having a low resistance are provided.
In the semiconductor device according to the twelfth aspect of the present invention, the isolation oxide film which is formed only on the second regions is small in area, to prevent the generation of dishing during the manufacture. Additionally, the first and second groups of SOI regions which constitute diodes are simple in construction.
In the semiconductor device according to the thirteenth aspect of the present invention, each of the second group of SOI regions has the silicide film formed on the upper surface thereof. Therefore, the SOI regions having a low resistance are provided.
In the semiconductor device according to the fourteenth aspect of the present invention, the second group of SOI regions are arranged in a matrix, with the isolation oxide film therebetween. Therefore, a substantial change in the positioning of the conductive portion of the shield layer is made by changing the configuration of an interconnect line for connecting the second group of SOI regions.
In the semiconductor device according to the fifteenth aspect of the present invention, the second group of SOI regions are electrically connected to each other by the gate interconnect line similar in construction to a gate electrode of a MOS transistor. This simplifies the step of manufacturing the interconnect line for electrical connection between the SOI regions.
In the semiconductor device according to the sixteenth aspect of the present invention, the gate structure of the MOS transistor is disposed on each of the first group of SOI regions. When a portion constructed by the first and second groups of SOI regions is regarded as a first resistive element, the gate structure of the MOS transistor is regarded as a resistive element disposed in parallel to the first resistive element. This further reduces the resistance of the shield layer.
In the semiconductor device according to the seventeenth aspect of the present invention, the gate structure of the MOS transistor is disposed on each of the second regions, and the SOI regions on the opposite sides of the gate structure have different conductivity types. Therefore, if a gate potential is applied to the gate structure, the gate structure does not function as a gate. This provides increased flexibility in selecting potentials to be applied to the gate structure.
In the semiconductor device according to the eighteenth aspect of the present invention, each of the second group of SOI regions and the first regions has the silicide film formed thereon selectively for non-engagement with the second regions. Therefore, the resistance of the shield layer is decreased.
In the semiconductor device according to the nineteenth aspect of the present invention, each of the first group of SOI regions has the silicide film formed thereon selectively for non-engagement with the second group of SOI regions. Therefore, the resistance of the shield layer is decreased.
In the semiconductor device according to the twentieth aspect of the present invention, the substrate portion of the SOI substrate comprises the eddy current suppressing portion having at least one hollow structure formed therein to suppress the generation of the eddy current induced by the inductance element in the substrate portion, thereby reducing the electromagnetically induced power dissipation.
In the semiconductor device according to the twenty-first aspect of the present invention, the eddy current suppressing portion comprises the cavity having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the cavity being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed. Therefore, the cavity prevents the eddy current from being induced by the inductance element in the substrate portion.
In the semiconductor device according to the twenty-second aspect of the present invention, the eddy current suppressing portion comprises the porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed. Therefore, the porous layer interrupts the path of the eddy current induced by the inductance element in the substrate portion, to avoid the electromagnetically induced power dissipation resulting from the eddy current.
In the semiconductor device according to the twenty-third aspect of the present invention, the SOI layer comprises the porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed. Therefore, the porous layer interrupts the path of the eddy current induced by the inductance element in the SOI layer, to avoid the electromagnetically induced power dissipation resulting from the eddy current.
In the semiconductor device according to the twenty-fourth aspect of the present invention, the semiconductor substrate comprises the porous layer having a depth which is a factor of about one to about ten less than the length, as viewed in plan, of the inductance element, the porous layer being approximately coextensive, as viewed in plan, with at least the region in which the inductance element is formed. Therefore, the porous layer interrupts the path of the eddy current induced by the inductance element in the semiconductor substrate, to avoid the electromagnetically induced power dissipation resulting from the eddy current.
The semiconductor device according to the twenty-fifth aspect of the present invention has a construction in which the porous layer is implementable.
The semiconductor device according to the twenty-sixth and twenty-seventh aspects of the present invention can reduce the electrostatically induced power dissipation by means of the shield layer, and interrupt the path of the eddy current in the shield layer to reduce the electromagnetically induced power dissipation. Additionally, the semiconductor device further comprises the plurality of trenches extending through the buried oxide film into the substrate portion. The plurality of trenches interrupt the path of the eddy current induced by the inductance element in the buried oxide film and the substrate portion, to avoid the electromagnetically induced power dissipation resulting from the eddy current.
The semiconductor device according to the twenty-eighth aspect of the present invention can reduce the electrostatically induced power dissipation by means of the shield layer formed in a so-called bulk substrate, and interrupt the path of the eddy current in the shield layer to reduce the electromagnetically induced power dissipation. Additionally, the semiconductor device further comprises the plurality of trenches extending into the substrate. The plurality of trenches interrupt the path of the eddy current induced by the inductance element in the buried oxide film and the substrate portion, to avoid the electromagnetically induced power dissipation resulting from the eddy current.
In the semiconductor device according to the twenty-ninth aspect of the present invention, the plurality of holes or trenches are filled with a near-vacuum, to interrupt the path of the eddy current induced by the inductance element and to reduce the electrostatically induced power dissipation.
In the semiconductor device according to the thirtieth aspect of the present invention, the plurality of trenches are filled with a near-vacuum, to interrupt the path of the eddy current induced by the inductance element and to reduce the electrostatically induced power dissipation.
The semiconductor device according to the thirty-first aspect of the present invention comprises the shield layer disposed in the main surface of the semiconductor substrate under and longitudinally of the interconnect layer, to reduce the electrostatically induced power dissipation resulting from the interconnect layer.
In the semiconductor device according to the thirty-second aspect of the present invention, each of the plurality of conductive portions comprises the plurality of conductor films and the plurality of insulation films stacked in an alternating pattern, to prevent current flowing in the interconnect layer from generating the eddy current in a plane perpendicular to the semiconductor substrate in the conductive portions, thereby avoiding the electromagnetically induced power dissipation resulting from the eddy current.
In the method according to the thirty-third aspect of the present invention, the cavity for suppressing the generation of the eddy current induced by the inductance element is efficiently formed in the region in which the inductance element, e.g. a spiral inductor, of the substrate portion of the SOI substrate is to be formed.
In the method according to the thirty-fourth aspect of the present invention, the porous layer for suppressing the generation of the eddy current induced by the inductance element is efficiently formed in the region in which the inductance element, e.g. a spiral inductor, of the substrate portion of the SOI substrate is to be formed.
In the method according to the thirty-fifth aspect of the present invention, the porous layer for suppressing the generation of the eddy current induced by the inductance element is efficiently formed in the region in which the inductance element, e.g. a spiral inductor, of the SOI layer of the SOI substrate is to be formed.
In the method according to the thirty-sixth and thirty-seventh aspects of the present invention, there is provided a specific method of rendering hollow the interior of the porous layer formed by etching.
In the method according to the thirty-eighth and thirty-ninth aspects of the present invention, there is provided a specific method of rendering hollow the interior of the porous layer formed by the anodization process.
It is therefore an object of the present invention to provide a semiconductor device having an inductor which is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation while preventing the structure and manufacturing steps thereof from becoming complicated.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.